Triggering of Flip Flops Objective Questions

The flip-flops which has not any invalid states are

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is

What does the triangle on the clock input of a J-K flip-flop mean?

How many stable states a combinational circuits have?

The S-R latch composed of NAND gates is called an active low circuit because

The only difference between a combinational circuit and a flip-flop is that

In a J-K flip-flop, if J=K the resulting flip-flop is referred to as

What does the circle on the clock input of a J-K flip-flop mean?

What does the direct line on the clock input of a J-K flip-flop mean?

The flip-flop is only activated by

In J-K flip-flop , the function K=J is used to realize

The characteristic equation of J-K flip-flop is

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

What does the half circle on the clock input of a J-K flip-flop mean?

Both the J-K & the T flip-flop are derived from the basic