Online TestTriggering of Flip Flops Objective Questions Triggering of Flip Flops Objective Questions Digital Electronics Objective Questions 0% The flip-flops which has not any invalid states are S-R, J-K, T J-K, D, S-R S-R, J-K, D J-K, D, T Correct!Wrong!- Continue >> What does the half circle on the clock input of a J-K flip-flop mean? Level triggered Positive edge triggered Level enabled negative edge triggered Correct!Wrong!- Continue >> In J-K flip-flop , the function K=J is used to realize T flip-flop D flip-flop None of the Mentioned S-R flip-flop Correct!Wrong!- Continue >> In a J-K flip-flop, if J=K the resulting flip-flop is referred to as None of the Mentioned D flip-flop T flip-flop S-R flip-flop Correct!Wrong!- Continue >> Both the J-K & the T flip-flop are derived from the basic D flip-flop S-R flip-flop D latch S-R latch Correct!Wrong!- Continue >> The characteristic equation of J-K flip-flop is Q(n+1)=J’Q(n)+KQ'(n) None of the Mentioned Q(n+1)=JQ(n)+K’Q(n) Q(n+1)=JQ'(n)+KQ(n) Correct!Wrong!- Continue >> The only difference between a combinational circuit and a flip-flop is that None of the Mentioned The flip-flop requires next state The flip-flop requires previous state The flip-flop requires a clock pulse Correct!Wrong!- Continue >> The S-R latch composed of NAND gates is called an active low circuit because It is only activated by a positive level trigger It is only activated by a negative level trigger It is only activated by either a positive or negative level trigger None of the Mentioned Correct!Wrong!- Continue >> What does the circle on the clock input of a J-K flip-flop mean? Level triggered negative edge triggered Level enabled Positive edge triggered Correct!Wrong!- Continue >> A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is A 10 kHz square wave Constantly HIGH Constantly LOW A 20 kHz square wave Correct!Wrong!- Continue >> What does the direct line on the clock input of a J-K flip-flop mean? Level triggered Positive edge triggered Level enabled negative edge triggered Correct!Wrong!- Continue >> What does the triangle on the clock input of a J-K flip-flop mean? Level enabled Level triggered Edge triggered Both Level enabled & Edge triggered Correct!Wrong!- Continue >> On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________ The clock pulse is HIGH The clock pulse is LOW The clock pulse transitions from LOW to HIGH The clock pulse transitions from HIGH to LOW Correct!Wrong!- Continue >> How many stable states a combinational circuits have? 2 4 3 5 Correct!Wrong!- Continue >> The flip-flop is only activated by Either positive or Negative edge trigger Negative edge trigger None of the Mentioned Positive edge trigger Correct!Wrong!- Continue >> Share the quiz to show your results ! Facebook Facebook Just tell us who you are to view your results ! Show my results >> Triggering of Flip Flops I got %%score%% of %%total%% right ↺ PLAY AGAIN ! Share With Your Friends Facebook Twitter LinkedIn Pinterest Email WhatsApp
