700+ VLSI Projects for Engineering Students

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In this blog, we listed VLSI Projects for engineering students based on VHDL, MATLAB, Verilog, Xilinx Software, and IEEE projects.

VLSI Projects

VLSI Projects for Engineering Students
S.No.VLSI Projects
1Adaptive Hold Logic for Aging-Aware Reliable Multiplier Design.
2Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.
3Performance and Power Exploration in Binary64 Division Units.
4Digital Phase-Locked Loop Supply Noise Cancellation with An All-Digital Approach.
5Ultra-Low-Voltage Asynchronous Delta Sigma Modulator in a 130-nm Digital CMOS Process.
6Speculative Adder: Inexact High-Speed and Low-Power VLSI Architecture
7Structured Visual Approach to GALS Modeling and Verification for Communication Circuits
8Quantum-Dot Cellular Automata X-bit x 32-bit SRAM Design.
9FPGA-Based FIR Filter Design
10Efficient Systolic Array Architecture Design for DWT.
11ASIC Design and Implementation of a High-Speed RSA Encryption Processor.
12Scalable NoC Microprocessor with 2.5D Integrated Memory and Accelerator
13Technology Optimized LUT Based Bit-Parallel Multiplier for FPGAs.
14Optimized 3×3 Shift and Add Multiplier Implementation on FPGA
15Caching Partitioned Reconfigurations in Reconfigurable Systems for Hardware Support.
16Reconfigurable Systems’ MAC Unit Enhancement Using Multi-Operand Adders.
17Binary to RNS Converter Design for jn-Bit Dynamic Range Using Arithmetic Based Modulo.
18ASIC Implementation of a Low-Latency Logarithmic Number System Unit.
19Design of a High-Speed VLSI Architecture for QR Decomposition in MIMO Systems.
20Fast Decoding Design for Critical Bits Using Single Error Correction Codes.
21Systematic Cell Design Methodology for Energy and Area Efficient XOR/XNORs.
22Cryptographic Multifunction Residue Architectures.
23Architecture for Dual-Mode Double Precision Floating Point Division
24Functional Broadside Test Generation for Integrated Circuits.
25Low-Power CMOS Circuit for Piezoelectric Energy Harvesting
26VLSI Architecture for Efficient Implementation of Bilinear Interpolation in Image Processing.
27Recursive Discrete Fourier Transform: Software Implementation
28Self-Healing Strategy for Cost-Effective Reliable Hardware Systems
29Ternary Logic Circuits Synthesis in Emerging Device Technologies
30Future VLSI Design: Ultra-Low Power Hybrid MTJ/CMOS Based Full-Adder
31Enhanced Built-In Self-Repair Techniques for Embedded Memories Yield and Reliability.
32FPGA-Based Bit Error Rate Performance Measurement in Wireless Systems.
33SDC-SDF Architecture for Pipelined Radix-2 FFT with Normal I/O.
34PEVA Strategy for Lifetime Extension of NAND Flash.
35Key Distribution Server Based Data Security Scheme VLSI Implementation for RFID System.
36Merging Functional Broadside Test Cubes for Low Power Test Generation.
37Bandwidth Efficient QPSK Modulator Design for Low Power VLSI Implementations.
38High-Speed All-Pass Transformation-Based Variable Digital Filters Design.
39Novel Cross Parity Codes for Low-Complexity Multiple Error Correcting Architectures.
40FPGA Configuration Frames Correction: Low-Cost Multiple Bit Upset.
41Revisiting Reversible Booth’s Multiplier for Enhanced Performance.
42CMOS Receiver Design for Dual Use of Power Lines in Design-for-Testability.
43Combining kPartitioning Scheme and TMVP Block Recombination in Digit-Serial Multipliers.
44VLSI Decoder Energy Consumption Analysis.
45Comparative Analysis of 16-order FIR Filter using Various Multiplication Techniques
46Flip Flop Grouping in Data Driven Clock Gating Design Flow.
47Multi Precision Adders: Improving Arithmetic Operations.
48FFT/IFFT Blocks Implementation for OFDM.
49Enhanced Double Precision Floating Point Multiplier Implementation Using VHDL.
50Vmin Failure Bias-Induced Healing in Advanced SRAM Arrays
51High-Speed ASIC Implementation of a Lossless Data Compression Algorithm for Space Applications.
52High-Level Transformations for Obfuscating DSP Circuits.
53Design of All Optical Reversible Multiplexer with Mach-Zehnder Interferometer.
54Distributed Arithmetic for Approximate Sum-of-Products Design
55Weighted Partitioning in Multiplier-less Multiple Constant Convolution Circuits.
56High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming.
57Binary Multiplier Design with a Memristor-Based Approach
58Mixed-Precision Multiply-Accumulate Unit Design for Deep Learning Processors
59Energy-Efficient FPGA Implementation of a Real-Time Neural Network-Based Speech Recognition System.
60Convolutional Neural Networks: Low-Power Implementation of Mitchell’s Approximate Logarithmic Multiplication
61Fault Tolerant Logic Cell Design for FPGA Applications
62Adaptive Feedback Equalization for Designing Tunable Subthreshold Logic Circuits.
63Advances in Logic Synthesis for Reversible Programmable Logic Arrays.
64FPGA Implementation of a High-Efficiency Video Codec (HEVC) for 4K Video Streaming.
65Architectural Design for a High Throughput Polar Codes List Decoder.
66Architecture for Long Polar Codes with Partial Parallelism.
67Efficient Adder Design for Approximate Computing with Configurable Accuracy
68Low-Power Broad-Bandwidth Noise Cancellation Circuit Design for In-Ear Headphones.
69ASIC Design of a High-Efficiency Turbo Code Encoder for Telecommunication Systems.
70Safety-Critical Applications: FPGA Implementation of an Improved Watchdog Timer
71VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm.
72Spurious-Power Suppression Technique for Multimedia/DSP Applications.
73Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT.
74Digital Multiplierless Realization of the Two-Coupled Hindmarsh–Rose Neuron Model.
75ASIC Design of a High-Performance Real-Time Video Codec for Virtual Reality Applications.
76High-Performance VLSI Architecture for Reed-Solomon Decoders.
77Circuit Complexity Reduction in Fractional-Order Differentiators and Integrators
78ASIC Implementation of a Low-Power High-Efficiency GPS Signal Processing Core.
79Design of a VLSI Architecture for Real-Time Video De-Interlacing.
80Rail Clamp Design Using Comparator-Based Approach.
81FPGA Integer Arithmetic Core Optimization through Efficient Scan Register Insertion.
82FPGA-Based Implementation of a Real-Time Multi-Sensor Data Fusion System.
83Non-Redundant Radix-4 Signed-Digit Encoding in Pre-Encoded Multipliers.
84High-Speed, Energy-Efficient Carry Skip Adder for Broad Voltage Level Operation.
85Enhanced Memory Reliability with Decimal Matrix Code Against Multiple Cell Upsets.
86FPGA-Based VLSI Architecture for Real-Time Optical Flow Estimation in Autonomous Vehicles.
87VLSI Design of a High-Speed Floating-Point Unit for Scientific Computing.
88Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput
89VLSI Architecture for a High-Speed Real-Time Hough Transform Processor.
90Flexible Memory BIST Architecture Design
91Radix-4 Memory-Based FFT Utilizing DSP Slices for Efficient Implementation
92Nano scale Circuit Design with Low-Power Noise-Immune Methodology Using Coding-Based Partial MRF
93Logarithmic Multipliers for Low Power Error-Tolerant Applications
94Low Complexity Implementation of LMS Adaptive Algorithm via Critical-Path Analysis.
9532-Bit 4×4 Bit-Slice RSFQ Matrix Multiplier for Rapid Processing
96Track-and-Hold Amplifier with 55-GHz Bandwidth in Low-Power 28-nm CMOS.
97Highly Accurate Analog Multiplier Circuit in Voltage Mode Implementation.
98Approximate High-Radix Dividers Design and Efficient Implementation
99Implementing Low Power 1-Bit Full Adder Utilizing Full-Swing Gate Diffusion Input Technique
100Chip Design for Turbo Encoder Module Targeting In-Vehicle Systems
101ASIC Design of a Low-Power High-Resolution Digital to Analog Converter for IoT Devices.
102ASIC Implementation of a High-Speed Optical Flow Calculation Processor.
103Super Gate Design Methodology for Graph-Based Transistor Network Generation.
104OFDM Transmitter Design and Implementation in VHDL.
105Combinational Logic Implementation in Successive Cancellation Decoders for Polar Codes.
106Dual-Supply Applications: High-Speed Power-Efficient Voltage Level Shifter Design
107FM0/Manchester Encoding for DSRC Applications Using SOLS Technique.
108Convolution and Deconvolution High-Speed Algorithm.
109Performance Degradation Tolerance in Cache Design by Exploiting Memory Hierarchies.
110Programmable Test-per-Scan Logic BIST Modules Designing for Efficiency
111Area-Efficient SCL Polar Decoder Optimization.
112Error-Tolerant Approximate Radix-4 Booth Multipliers Design
113Fixed and Reconfigurable Applications: A High-Performance FIR Filter Architecture.
114Min-Sum LDPC Decoding for MLC NAND Flash with Intracell Bit-Error Exploitation.
115Error Correction Code-Based Fault Tolerant Parallel Filters.
116Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials
117Sequential Observation in POST for Automotive Functional Safety Assurance
118Fundamental Energy Limits Enhancement in Field-Coupled Nano computing Circuits
119Efficiency Retiming in Fixed-Point Circuits.
120Static D-Latch Standard Cell Characterization Using an Efficient Setup Time Model.
121High-Speed VLSI Architecture for Real-Time Processing of Synthetic Aperture Radar Data.
122FPGA Implementation of a Real-Time Digital Video Stabilization Algorithm.
123High-Speed Parallel LFSR Architectures Based on State-Space Transformations
124Scalable Deep Learning Accelerator Unit on FPGA
125Approximate 15-4 Compressor Multiplier Design and Analysis
126Radix 8 Booth Multipliers with a Slack-based Pipeline Architecture for High Performance.
127Area Efficient Reconfigurable Multimode Interleaver Address Generator for Radios.
128PRAM Lifetime Improvement with Process Variation Considerations.
129FPGA-Based Implementation of a High-Speed Optical Character Recognition System.
130FPGA Implementation of Compressor-Based Vedic Multiplier.
131Energy Dissipation Analysis in Quantum-Dot Cellular Automata Logic Gates.
132Deadlock-Free ID Assignment in Advanced Interconnect Protocols for High Performance.
133High-Speed VLSI Architecture for DCT-Based Feature Extraction in Image Recognition.
134Voltage-Scaled Clock Distribution Networks Design Methodology.
135Encrypted Images: Lossless and Reversible Data Hiding with Public Key Cryptography.
136Efficient Modulo 2n+1 Multiply Add Add Units Design and Implementation.
137FPGA-Based Real-Time Object Tracking System for Surveillance Applications.
138Novel Components and Methodology for Reverse Converter Design via Parallel-Prefix Adders.
139Efficient BCD Adders Design in Quantum Dot Cellular Automata.
140Error Correction Protocols for Silicon PUF Responses using Key Reconciliation
141FPGA-Based Reconfigurable FIR Filter Design.
142Efficient Residue Number System Scalers for Extended Three-Moduli Set
143Low-Power Weighted Pseudorandom Test Pattern Generation for Scan-Based BIST
144RNS Comparison Enhancement via Dynamic Range Partitioning.
145Low-Complexity Digit-Serial Multiplier Over GF(2m) Using Toeplitz Block-Toeplitz Decomposition
146VLSI Design for an ASIC-Based Real-Time Speech Recognition System.
147Montgomery Modular Multiplication: High-Performance VLSI Architectures.
148Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline.
149Integer Transform Architecture VLSI Design for HEVC
150Design of Area-Power Efficient FIR Filters with Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm
151FPGA Implementation of a Multi-Standard Video Format Converter.
152Performance Evaluation of Fixed-Width Modified Baugh-Wooley Multiplier on FPGA.
153Modified Partial Product Generators in Redundant Binary Multipliers.
154Power and Area Efficient Approximate Multiplier Designs
155ASIC Implementation of a High-Speed Digital Predistortion Processor for RF Power Amplifiers.
156CMOS PWM Transceiver Utilizing Self-Referenced Edge Detection.
157Single Layered Logic Generator Block Design and Simulation Using Quantum Dot Cellular Automata.
158High Speed Computing: Low Power Multiplier Architectures Using Vedic Mathematics.
159Fast Carry Chains in FPGAs for Approximate Quaternary Addition
160HEVC Standard’s Low Power Approximate DCT Architecture
161FPGA-Based Implementation of Multi-Precision Floating Point Arithmetic Unit
162Built-In Redundancy Analysis for Memory with Various Spare Hardware-Efficient Designs
163Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm
164Unequal-Error-Protection Codes for Embedded Memory in DSPs.
165CMOS Chopper Analog Multiplier with Four-Quadrant Functionality
166FPGA Implementation of Pipeline Large-FFT Processor for Operating Frequency Improvement
167Vertical-Horizontal Binary Common Sub-expression Elimination for Efficient FIR Filter Synthesis.
168Energy-Efficient VLSI Design for a Biometric Recognition System Based on Iris Patterns.
169Rail-to-Rail Input Range Low-Power ASK Detector for Minimal Modulation Indexes.
170Configurable Adder Design for Approximate Computing Applications
171Approximate Circuits Design by Gate-Level Pruning
172Low Power ECG Acquisition System with Fully Digital Architecture.
173VLSI Design of a High-Speed Real-Time Phase Unwrapping Processor for SAR Imaging.
174Energy Efficiency in Radix-16 Sequential Multiplier Designs
175Adaptive Filters with Error Nonlinearities: Algorithm and Architecture
176Compact Digital Circuits: High-performance Engineered Gate Transistor-Based
177Reconfigurable FPGA Approach for Adaptive Median Filtering: Impulse Noise Suppression.
178VLSI Architecture for an Efficient Implementation of the K-Means Clustering Algorithm.
179Energy-Efficient VLSI Design of a Digital Stethoscope for Heart Rate Monitoring.
180Data-Controlled Segmentation in Parallel Pseudo-Exhaustive Testing of Array Multipliers
181Architecture Generation for Type-3 Unum Posit Adder/Subtractor
182Subthreshold SRAM Cell Design with Dynamic Feedback Control in Single-Ended 8T.
183Bit-Level Optimization for Multiple Constant Multiplications in FIR Filter Implementation.
184Test Versus Security: Analyzing Past and Present Challenges.
185Energy-Efficient VLSI Architecture for Real-Time Video Encryption.
186FPGA-based Reconfigurable Constant Multiplication
187Ternary Multiplier Analysis Using Booth Encoding Technique.
188Integer DCT Architectures for High Performance in HEVC
189Bus Bridge Design between OCP and AHB Protocol.
190Low-Power Processor Design for Predicting Ventricular Arrhythmia using ECG.
191Designing a Low Power 4×4 Bit Multiplier using Dadda Algorithm with an Optimized Full Adder
192Area-Time Efficient FFT-Based Montgomery Multiplication Architecture
193Polar Codes: Efficient Soft Cancelation Decoder Architectures
194Energy-Efficient TCAM Search Engine Design with Priority-Decision Memory Technology
195Speed Binning Using On-Chip Ring Oscillators in Statistical Framework and Built-In Self System.
196Design of a VLSI Circuit for Real-Time Electrocardiogram QRS Detection.
197Statistical Analysis of MUX-Based Physical Unclonable Functions for Secure Hardware Design.
1983-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation.
199Low Power Neuromorphic Integrated Circuit Tolerant to Device Mismatch.
200Design of a High-Speed VLSI Architecture for Real-Time Histogram Equalization.
201VLSI Implementation of a Configurable High-Speed LDPC Codec for Broadband Communications.
202Efficient Parallel Decoder for the Extended Golay Code with Single and Double-Adjacent Error Correction.
203Distributed Embedded Multiprocessors: Efficient Synchronization.
204memristor-CMOS Hybrid Look-up-table Design and Application in FPGA
205Power and Area Efficient Digital FIR Filter with Modified MAC Unit.
206VLSI Architecture for Efficient Implementation of the Smith-Waterman Algorithm.
207Creation of Faithfully Rounded Truncated Multipliers and Arrays.
208MIGFET Devices Utilization in Binary Adder Circuit Design
209Unity-Gain SDF-FFTS with Multiplier less Architecture
210Mixed-Logic Line Decoders: Low Power, High-Performance 2-4 and 4-16 Designs
211Approximate Adder Design with Optimized Lower Part Constant-OR
212GALS Modelling and Verification Structured Visual Approach for Communication Circuits
213FPGA Implementation of a Convolutional Neural Network Accelerator for Real-Time Object Detection.
214Advance Microcontroller Bus Architecture Analysis and Implementation on AHB Bridge.
215Montgomery Modular Multiplication: Low-Cost High-Performance VLSI Architecture.
216Implementation of Binary to Gray Code Converter Using Quantum Dot Cellular Automata
217Optimizing Constant Vector Multiplication with Improved Signed Digit Representation.
218High-Speed Computing Using Low Power Vedic Mathematics in 45nm Technology Multipliers.
219Energy-Efficient Inexact Multipliers with Hybrid High Radix Encoding
220Extending Orthogonal Latin Square Codes for Enhanced Error Correction.
221Square Computation Using Dedicated Reversible Quantum Circuitry.
222Precision-Oriented Low-Power High-Speed Comparator for Accurate Applications
223VLSI Design of a High-Performance Gabor Filter for Texture Analysis.
224High-Throughput Energy-Efficient Decoder Architectures for Belief Propagation in Polar Codes
225FM0/Manchester Encoding VLSI Design with SOLS Technique for DSRC Applications.
226Efficient Non-binary LDPC Codes Decoding with Extended Min-Sum Algorithm.
227Probabilistic Error Modeling for Approximate Adder Circuits
228VLSI Implementation of a High-Speed Coherent Demodulator for Digital Communication Systems.
229Innovative QCA Threshold Gate with Five-Input Multiple-Function
230Integer DCT Architectures Tailored for High Efficiency Video Coding.
231Efficient Design of the Add-Multiply Operator Using Optimized Modified Booth Recoder.
23264-bit Radix-16 Booth Multiplier with Improved Partial Product Array
233High-Speed Floating Point Multiplier Design Using Karatsuba Algorithm.
234Fully Digital Front-End ECG Acquisition Architecture with Ultra-Low Voltage Operation
235Dynamic Circuit Technique for Low-Power Microprocessors Using Flexible Charge Recycling.
236Overloaded CDMA Crossbar Architecture for Network-On-Chip
237VLSI Architecture for Radix-2 Modified Booth Algorithm in Parallel Multiplier Accumulator.
238Improved Fixed-Width Adder-Tree Efficiency
239Low-Power High-Speed TI-SAR ADC with High SNDR in 65-nm CMOS Technology
240Signal Feed-Through Scheme Based Low-Power Pulse-Triggered Flip-Flop Design.
241Quantum-Dot Cellular Automata Based Novel SRAM Design.
242Low Switching Power and Ultra-Low RBL Leakage in 10T SRAM with Half-VDD Precharge
243Logic Generator Block Design Using Quantum Dot Cellular Automata in a Single Layer.
244High-Speed FPGA Implementation of ECC Processor Based on RSD.
245Quantum Dot Cellular Automata Based Flip-Flop Circuits: A Novel Approach
246CWFP: Collective Write back and Fill Policy for DRAM Cache.
247Energy-Efficient ASIC Design for a Portable Real-Time Electroencephalogram Monitoring System.
248Extended Four-Moduli Set Residue-to-Binary Converter Design
249Innovative CDMA Encoding/Decoding Method for On-Chip Communication Networks.
250Analysis and Design of Inexact Floating-Point Adders.
251Nano scale CMOS Technology-based 12T Memory Cell for Aerospace Applications
252LLR-based List Decoder for Polar Codes with Multi-bit Decision
253FPGA-Based Architecture for Real-Time Sobel Edge Detection.
254High-Speed Accuracy-Controllable Approximate Multiplier
255Hybrid Test Points in Logic Built-In Self-Test with Capture-per-Clock
256Single Layered Logic Generator Block Design Using Quantum Dot Cellular Automata.
257Sense Amplifier Half-Buffer: High-Performance Asynchronous Logic QDI Cell Template
258Advanced Encoding and Decoding Architecture of Polar Codes on FPGA.
259Compressor-Based MAC Architecture for Low Power DSP Applications.
260Multiple Error Correcting Architecture Using Cross Parity Codes Over GF(2m).
261Pipeline Timing Errors One-Cycle Correction with Standard Clocked Elements.
262Generalized Efficient Conflict-Free Address Schemes in Memory-Based FFT Processor Design
263Squaring Algorithm Enhancement Using an Implicit Arbitrary Radix Number System.
264Power Dissipation Minimization in Digital Circuits Using Rule-Based Approach.
265Probabilistic Gradient Descent Bit-Flipping’s Efficient Hardware Implementation
266Energy-Efficient Data Processing in loT Sensors with Inexact Arithmetic Circuits
267Challenges in Trojan Insertion for Reversible Computing Architectures
268Low Power 16-bit RISC Processor Using Advanced Pipelining Techniques.
269LMS Adaptive Algorithm: Critical Path Analysis and Low Complexity Implementation.
270FPGA-Based Implementation of a High-Speed Network Packet Processor.
271Majority Logic Formulations for Parallel Adder Designs Reducing Delay and Circuit Complexity
272High-Speed 256-Bit Carry Look Ahead Adder in 22nm Strained Silicon Technology.
273Securing Scan-Based Attacks on Secure-ICs with On-Chip Comparison.
274A Fast-Acquisition All-Digital Delay-Locked Loop with Starting-Bit Prediction Algorithm.
275STT-RAM Performance Barrier Analysis with Read Performance Consideration.
276ASIC Design of a Low-Power High-Efficiency Wireless Charger Transmitter Controller.
277Built-in Self-Calibration Technique for ±1 LSB INL in 14-Bit SAR ADCs.
278Improved Diagnostic Abilities and Logic Testing with Test-per-Clock Pattern Loading
279Efficient VLSI Architecture for Convolution Based DWT Using MAC
280Ultra-low-Energy Adder Designs: A Variation-Aware Study.
281Low-Power Unsigned Divider Design with Adaptive Approximation
282High-Yield 5 nm Underlapped FinFET SRAM Design with P-Type Access Transistors.
283Architecture for Nonbinary LDPC Codes with Min–Max Decoder for Trellis and High-Order Galois Fields
284Scalable Approximate DCT Architectures for Efficient HEVC Compliant Video Coding
2858-bit Microcontroller Design in VHDL.
286Boolean Logic Circuits Mapping Methodology on Memristor Crossbar
287Deep Learning Accelerator Unit on FPGA – DLAU
288Solving RF-SoC Integration in Multichannel Systems Through Digital Fractional Division.
289VLSI Implementation of DA-Based Reconfigurable FIR Digital Filter.
290ASIC Design of a Low-Power High-Resolution Magnetometer for Navigation Systems.
291Energy-Efficient Carry Skip Adder Operating Across Supply Voltage Levels.
292VLSI Architecture for High-Speed Computation of the Discrete Hartley Transform.
293FPGA-Based Implementation of a Real-Time Adaptive Beamforming System for Radar Applications.
294Implementing a 16×16 Multiplier Using Vedic Mathematics for Enhanced Speed.
295Design of a Versatile Multimedia Functional Unit Using Spurious Power Suppression Technique.
296Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding.
297FPGA-Based VLSI Architecture for Matrix Inversion Using Gauss-Jordan Method.
298VLSI Implementation of a Low-Complexity Bio-Signal Processor for Portable Health Monitoring Devices.
299Majority Logic-Based Field-Coupled QCA Nano computing Adder and Subtractor Circuit Design.
300Latch-Type Sense Amplifier Modification in 28-nm for Coupling Suppression
301FPGA Implementation of Reconfigurable Channelization Architecture for SDR Applications.
302LUT-Based Multiplier Approach for Short Word Length DSP Systems
303MIMO Baseband Processing: Efficiency Enablers of Lightweight SDR.
304Improving Defect Diagnosis Accuracy with A Test Selection Procedure.
305Energy-Efficient FPGA Implementation of a Real-Time Eye Gaze Tracking System.
306Current-Mode Clock Synthesis (CMCS) Design
307Floating-Point Expansions in Extended Precision Arithmetic Algorithms.
308Dual-Quality 4:2 Compressors for Dynamic Accuracy Configurable Multipliers.
309Separated Dictionaries in Code Compression for Embedded Systems.
310FPGA-Based Implementation of a High-Speed Network Traffic Management Processor.
311Power Reduction in Dynamic Systems Using Scenario-Aware Bias Addition Technique
312Low-Power Design Using Encoded Partial Products in Approximate Multipliers
313Write Buffer-Oriented Energy Reduction in L1 Data Cache for Embedded Systems.
314Configurable Joint Detection and Decoding Architecture in MIMO Wireless Communications.
315Advancements in Pre-Encoded Multipliers with Non-Redundant Radix-4 Signed-Digit Encoding.
316Hardware Realization of Sum of Absolute Difference Component Generator
317Clock Gating Based on Auto Gated Flip Flops for Look Ahead.
318Nonvolatile Spintronic Flip-Flops: Design of Defect and Fault-Tolerant
319High-Speed and Low-Power Design Using Multiple Constant Multiplication Algorithm.
320Computation-in-Memory Parallel Adder Implementation
321Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units.
322Self-Motivated Arbitration Scheme Design for Multilayer AHB Busmatrix.
323Implementing Fast Radix-10 Multipliers for High-Speed Decimal Calculations.
324Delay Analysis in Current Mode Threshold Logic Gate Designs
325Adiabatic Quantum-Flux-Parametron Logic-Based Carry Look-Ahead Adder Families
326Gated Voltage Level Translator with Integrated High-Performance Multiplexer
327VLSI Architecture for Radix-Sort-Based Finding of First W Maximum/Minimum Values.
328Dynamic Feedback Control in Single-Ended 8T Sub-threshold SRAM Cell Design
329VLSI Design of a High-Resolution Time-to-Digital Converter for LIDAR Applications.
330FPGA Implementation of a High-Efficiency H.265/HEVC Decoder Module.
331Evolutionary Digital Circuits Design Approach for Approximation
332Multiple Page Sizes in NAND Flash Memory for High-Performance Storage Devices.
333JPEG Image Compression Standard Design.
334Digital Sensor Macros Network for Power Supply Noise Profile Extraction in SoCs.
335Energy-Efficient Approximate Multiplier Design with Logic Compression
336Low Latency Architecture for Matching Encoded Data with Hard Systematic Error Correcting Codes.
337Binary64 Division with Redundant Number Systems: Energy-Efficient VLSI Realization
338Lightweight AES S-box Design Using LFSR.
339Cooperative Jammer in MIMO Secrecy Channel: Secrecy Rate Optimization.
340Rapid Decoding Techniques for Single and Adjacent Error Correction Codes
341CRC Encoder and Decoder Design and Simulation with VHDL
342Efficient Binary Adder Designs Utilizing Quantum-dot Cellular Automata.
343Low-Voltage Low-Power Design of Double-Tail Comparator.
344Power Droop Reduction During Launch-On-Shift Scan-Based Logic BIST.
345Performance Enhancement in NB-LDPC Decoder with Reduced Message Exchange.
346Polynomial Weight Functions in a Novel Cellular Network Architecture.
347VLSI Design Considerations for Convolutive Blind Source Separation.
348Quantum-Dot Cellular Automata-Based Efficient Binary Comparators Design.
349ASIC Implementation of a Low-Power Face Detection Processor.
350Trigger-Centric Loop Mapping on Coarse-Grained Reconfigurable Architectures.
351Enhanced SRAM Cells with Half-Select-Free Design and Comprehensive BTI Analysis for Low Leakage
352Built-In Self-Repair Optimization for Multiple Memories.
353Distributed Arithmetic Based LMS Adaptive Filter for Area and Power Efficiency
354Area Efficient 1024-Point Radix-22 FFT Processor with Feed-Forward Multiple Delay Commutators
355Efficient One-Pass Seed Generation Method for LFSR-Based Testing.
356Low-Power Programmable PRPG with Enhanced Test Compression Capabilities.
357Coplanar Full Adder Design in Quantum-Dot Cellular Automata via Clock-Zone Based Crossover.
358Hybrid 1-bit Full Adder Circuit’s Low-Power High-Speed Performance Analysis
359Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration on FPGA.
360High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications.
361Area-Delay Efficient Adder Design in Quantum Dot Cellular Automata.
36216-bit QPSK (Quadrature Phase Shift Keying) Design.
363AES Encryption Algorithm Design with 128-bit Key Length.
364Xilinx System Generator Optimized for Sobel Edge Detection Technique.
365ARX-Based Cryptography Side-Channel Protected Processor Architecture – SPARX
366VLSI Architecture for Reconfigurable Pulse Shaping FIR Interpolation Filter in DUC.
367Variation-Tolerant Nonvolatile Low-Power Lookup Table Design.
368Modified Cosine-Based Comb Decimation Filters: Design, Analysis, and Implementation
369High-Speed VLSI Architecture for Integrated Image Enhancement and Edge Detection.
370Real-Time Electrical Capacitance Tomography: A New Parallel VLSI Architecture.
371Universal, Scalable, and Efficient Clocking Scheme for Quantum Dot Cellular Automata.
372Multi-Precision Floating Point Multiplier Design for High-Speed, Low-Power Applications.
373Adaptive Hold Logic in Aging Aware Reliable Multiplier Design.
374Extended Burst Error-Correction Codes with Quadruple Adjacent Error Correction Capability
375Parallel Prefix Adders: Design and Delay, Power, and Area Estimation.
376ASIC Implementation of a High-Speed Lattice Reduction Algorithm for MIMO Detection.
377Min–Max Decoder Architecture for Nonbinary LDPC Codes with Two-Extra-Column Trellis
378Low-Power Content-Addressable Memory Based on Sparse Clustered Networks.
379Energy-Efficient and Variation-Tolerant Design Considerations for Nonvolatile Logic
380Area-Delay-Power Efficient LMS Adaptive Filter with Fixed-Point Operations for VLSI Implementation.
381Novel Components and Methodology for Reverse Converter Design via Parallel Prefix Adders.
382Binary Signed-Digit Representation in Floating-Point Butterfly Architectures.
383Convolution Efficient FPGA Implementation.
384Utilizing Fast Radix-10 for Efficient BCD Multiplication.
385SEC-DED-DAEC Codes Derived from Orthogonal Latin Square Codes for Error Correction.
386Dual-Mode Double Precision Floating Point Division Architecture
387Energy-Efficient ASIC Design for a Real-Time Portable Ultrasound Imaging System.
388Complex Number Multiplier Design Using High-Performance Booth-Wallace Algorithm.
389Custom Accelerator Design for Homomorphic Encryption Applications
390High-Speed Configurable Adder for Approximate Applications
391Analyzing the Effect of Switched-Capacitor CMFB on Fully Differential OpAmp’s Gain for Integrator Design
392AES-like Block Ciphers: Countermeasures against Differential Fault Analysis
393Viterbi Decoder Design for Multi-Standard Receiver Optimization.
394Multi-operand Logarithmic Addition/Subtraction via Fractional Normalization
395LFSR-Based Test Generation from Non-Test Cubes: Computing Seeds.
396Sub-threshold Adiabatic Logic Implementation for Ultra-Low-Power Applications.
397Enhancing FFTs Fault Tolerance Using Error Correction Codes and Parseval Checks.
398Reversible Decoder Design in Xilinx Using Combinational Circuits
399High-Speed ASIC Implementation of a Multichannel EEG Signal Processing Unit.
400Digital Low-Power Baseband Processor Design for RFID Tags.
401High Performance 64-bit MAC Unit Design.
402Wide-Tuning-Range VCO Design with Frequency-Tuning Negative-Conductance Boosted Structure.
403Space Applications: Complementary Dual-Modular Redundancy Dynamic Memory for Area and Energy Efficiency
404Extending Orthogonal Latin Square Codes for Error Correction.
405Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers Power-Efficient Design.
406Reconfigurable FIR Interpolation Filter VLSI Architecture for Multistandard DUC.
407A Novel XOR-Free Approach in Convolutional Encoder Implementation.
408NULL Conventional Logic Without Registers
409Input Test Data Volume Reduction Techniques for Skewed-Load Tests.
410On-Chip Bus Design with OCP Interface.
411Design of a Low Power VLSI Architecture for Image Scaling in Portable Devices.
4128-bit ALU Design with Full Adder and Multiplexer for Low Power
413FPGA Implementation of a High-Dynamic Range Image Processing Unit.
414Parallel Self-Timed Adder Design Using Recursive Methods.
415Reliability and Performance in NAND Flash/SCM Hybrid Solid-State Drives.
416Scalable Microprogrammed FIR Filter Architectures Using Vedic Multipliers on FPGA.
417Efficient VLSI Architectures for Cryptographic Multifunction Residue Number System Operations.
418Low-Power Parallel Chien Search Architecture with a Two-Step Approach.
419Post-Silicon Skew Tuning with Fault Detection and Tolerance Architecture.
420FPGA Configuration Frames: Low-Cost Multiple Bit Upset Correction in SRAM-Based.
4218-bit RCA Adder Analysis Across Different Nanometer Regimes.
422Parallel Prefix Adders: Design and Delay Power Area Estimation.
423Byte-Reconfigurable LDPC Codec Design for ECC in NAND Flash Memory Systems.
424Design and Analysis of Truncated Ternary Multipliers.
425TM-RF: Aging-Aware Power-Efficient Register File Design in Modern Microprocessors.
426ASIC Implementation of a Low-Power High-Speed FFT Processor for OFDM Systems.
427High-Speed Current-Steering DAC with SUC-Based Full-Binary Design.
428Voltage Over-Scaling Limits for Error-Resilient Applications
429Efficient VLSI Implementation of a High Resolution D/A Converter for Audio Applications.
430High-Performance VLSI Architecture for Real-Time Wavefront Reconstruction in Adaptive Optics.
431Stereo Matching Enhancement with Error Resilient and Energy Efficient MRF Message-Passing.
432VLSI Design of Low-Cost and High-Precision FFT Processors
433Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA
434Xilinx System Generator for EEG Signal Denoising Using Wavelet Transform
435Low-Power Test Set Generation Based on Functional Broadside Tests.
436Wideband Low-Noise Amplifier Design Technique for Sub-mW Applications.
437Stochastic LU Decomposition Scheme for MIMO Receivers: Hardware and Energy Efficiency.
438New Hybrid Double Multiplication Architectures with Serial Out Bit Level Mastrovito Multiplier.
439Efficient Deployment of Radix 8 Booth Multipliers Using a Slack-based Approach.
440Enhanced Efficiency Passive Noise Shaping in SAR ADCs
441Montgomery Modular Multiplication: A VLSI Architecture for High-Performance and Low-Cost.
442Efficient Modular Adders Design with Reversible Circuitry
443Low Transistor Ternary CNTFET SRAM Cell: Design and Performance Evaluation.
444AMBA-Advanced High-Performance Bus (AHB) Protocol IP Block Design.
445Energy-Efficient VLSI Architecture for Pattern Matching in Network Intrusion Detection Systems.
446Power and Area Efficient LMS Adaptive Filter Design with Fixed-Point Arithmetic.
447Fast Computation and Low Complexity for Recursive MDCT and IMDCT Algorithms.
448A Parallel Radix-Sort-Based VLSI Architecture for High-Speed Applications.
449Low-Latency ECC Processor Implementation Over GF(2m) on FPGA
450High-Throughput Hardware Design for One-Dimensional SPIHT Algorithm.
451VLSI Design of a Low-Power and High-Accuracy GPS Baseband Processor.
452Dynamic Voltage Scaling Multiplier with Operands Scheduler for Power Efficiency.
453Aging-Aware Reliable Multiplier with Adaptive Hold Logic for Enhanced Performance.
454Efficient VLSI Realization of Decimal Multiplication with Sign-Magnitude Encoding
455ASIC and FPGA Benchmarked Reliable Low-Latency Viterbi Algorithm Architectures
456Reversible Decoder and Its Applications in Quantum-Dot Cellular Automata.
457SEC–DAEC Codes Implementation Optimization in FPGAs.
458On-Chip Power Management via Digitally Controlled Pulse Width Modulator.
459Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Using Stochastic Computing.
460Distributed RFID Systems: A Novel Coding Scheme for Secure Communications.
461Optimal Algorithm for Energy Saving in Embedded Systems with Multiple Sleep Modes.
462Energy-Efficient Data Encoding Techniques for Reducing the Power Consumption in Network-on-Chips.
463Binary Adders Efficiency Improvement in QCA.
464FIR Filter Design Based on Improved DA Algorithm and FPGA Implementation.
465O(N) Comparison-Free Sorting Algorithm: An Efficient Approach
466VLSI Architecture for High-Speed Computation of the Fast Walsh-Hadamard Transform.
467Fast Floating Point Multiplier Unit for High-Speed Applications.
468Resource Constraint Environments: Modified Advanced Encryption Standard (MAES)
469Efficient ASIC Implementation of CORDIC Algorithm for Wireless Communication Protocols.
470High-Performance VLSI Architecture for Real-Time Dynamic Scene Analysis and Reconstruction.
471Visible Watermarking Implementation in a Secure Still Digital Camera Using VLSI Design.
472Design of a Low-Power VLSI Circuit for Real-Time Ambulatory Cardiac Monitoring.
473Efficient FPGA Implementation of Intra Prediction in HEVC
474Cyclic Redundancy Check (CRC) Generator Design in Verilog.
475Bit Error Rate Performance Measurement of Wireless Systems Using Field Programmable Gate Arrays.
476High-Performance VLSI Architecture for Real-Time Image Segmentation Using Active Contours.
477Analog Equalizer with a Tunable and Current-Reusable Active Inductor for I/O Links.
478Energy Efficient Implementations of Streaming Applications on FPGAs via Clock-gating
479Adaptive Traffic Light Controller Using FPGA for Intelligent Control.
480Diagnostic Vectors Election from Detection Test Sets in COMEDI for Logic Circuits
481Enhancing Decimal Multipliers’ Performance Using Hybrid BCD Codes.
482VLSI Implementation of an Adaptive Noise Cancellation System.
483FPGA Implementation of a High-Performance Digital Predistorter for Wireless Transmitters.
484Design and Analysis of a Low Power Magnitude Comparator
485FPGA-Based Adaptive Filter Design for Noise Cancellation in Audio Signals.
486Dual-Clock VLSI Design for H.265 Sample Adaptive Offset Estimation Targeting 8k Ultra-HD TV Encoding
487Multi ported Memory Efficient Designs on FPGA
488Quantum-Dot Cellular Automata Based Efficient BCD Adders Design
489Recursive Multipliers Approximate Error Analysis
490Approximate Compressors for Energy-Efficient Multiplication Design and Analysis.
491Adaptive Logic Implementation for Minimum-Energy-Point Systems.
492Quaternary Logic Lookup Table Implementation in Standard CMOS.
493Scan Flip-Flop Design for High-Performance Serial and Mixed Mode Scan Test
494Permanent Faults In-Field Test for FIFO Buffers of NoC Routers.
495One-Dimensional Median Filter: A Low-Power VLSI Architecture.
496Design and Implementation of a Low-Power VLSI Circuit for ECG Signal Processing.
497Borrow-Save Adders for Low-Power Addition under Threshold Voltage Variability
498Reducing Hardware Complexity in Parallel Prefix Adders
499VLSI Architecture for a High-Speed Real-Time Fourier Transform Processor.
500Digital FM Receiver Construction Using Phase Locked Loop.
501ASIC Implementation of a High-Performance Digital Phase-Locked Loop.
502Energy-Efficient VLSI Architecture for the AES-GCM Encryption Standard.
50316-bit QAM Modulator Design.
504Design Methodology for Secure Differential Logic Gates to Enhance Circuit Security Against Differential Power Analysis Attacks.
505Memristor-Based Multipliers Optimization
506Redundant Representation Digit-Level Serial-In Parallel-Out Multiplier for Finite Fields
507ASIC Design of a Low-Power High-Speed True Random Number Generator.
508Vedic Multiplier Proposal with High-Speed Quaternary Signed Digit Number System
5092-D Lifting-based Discrete Wavelet Transform Efficient Architecture.
510Design of a VLSI Architecture for Real-Time Implementation of the Kalman Filter.
511Power Reduction in Launch and Capture Testing for SoCs.
512VLSI Design for a High-Performance Real-Time Image Denoising Processor.
513Fast Radix 10 Multiplication with Redundant BCD Codes.
514Power-Efficient High-Speed Multiplier Design Using Operands Scheduling for Dynamic Voltage Scaling.
515Exploiting Carry-Save Arithmetic in Flexible DSP Accelerator Architectures.
516Color Demosaicking VLSI Design: Fully Pipelined, Low-Cost, High-Quality for Real-Time Video Applications.
517Dynamically Reconfigurable Logic Gates in Single-Flux-Quantum Logic Circuits Design.
518Error Correction with Double Error Cellular Automata and Compact Syndrome Coding in Resilient PUF Design
519Low-Voltage Operation in 22-nm FinFET Technology Based Full-Swing Local Bitline SRAM Architecture.
520Combinational Circuits Optimization via Transistor-Level Reconfiguration
521MUX-Based Physical Unclonable Functions: Statistical Analysis.
522Normal I/O Pipelined Radix-2 FFT with Combined SDC-SDF Architecture.
523Cost Reduction in Triple Adjacent Error Correction of Orthogonal Latin Square Codes.
524Efficient Low-Power Forward and Reverse Body Bias Generator in 40 nm CMOS
525Optimizing Power-Accuracy Trade-off in Approximate Adders
526FPGA-Based VLSI Architecture for Real-Time Pedestrian Detection in Automotive Applications.
527Deadlock-Free ID Assignment in Advanced Interconnect Protocols with High Performance
528Double-Edged Pulse width Modulation Serial Communication with Source Coding and Preemphasis.
529High Throughput S-box for AES Application Using Multiplexers.
530VLSI Design for a Low-Power High-Performance FFT Processor in Communication Systems.
5313–5 GHz UWB Receivers: Band-Selective Low-Noise Amplifier with Improved Active Inductor
532Variable Digital Filters Design with Modified Second-Order Frequency Transformations.
533Versatile Reconfigurable Decoder for LDPC and Polar Codes
53464-bit Hybrid Adder Design with Low Voltage and Power Utilizing Radix-4 Prefix Tree Structure.
535BCH Codes One-Pass Chase Decoding: Error Locator Polynomial Searching Algorithm and Architecture.
536Low-Voltage Operation Optimized Sense-Amplifier-Based Flip-Flop Design
53732-bit RISC CPU Design Based on MIPS.
538Error Correction Codes in Fault Tolerant Parallel Filters.
539VLSI Design of a High-Performance and Low-Power SRAM Cache for Embedded Systems.
540Reduced Complexity Wallace Tree Multiplier for Power and Area Efficiency.
541Programmable Truncated Multiply and Accumulate for DSP with Razor-Based Energy Reduction.
542FPGA-Based VLSI Architecture for a Real-Time Adaptive Noise Reduction System.
5430.5 V Supply ECG Acquisition System with a Fully Digital Front-End Architecture.
544Modified Partial Product Generator for Efficient Redundant Binary Multipliers.
545Systematic Design of Faithfully Rounded Truncated Multipliers and Arrays.
546High-Speed DDR SDRAM Controller Design and Implementation.
547FPGA Implementation of 3D Discrete Wavelet Transform for Real-Time Medical Imaging.
548Reconfigurable Approximate Carry Look-Ahead Adder – RAP-CLA
549ASIC Design of a Low-Power High-Performance Correlator for Wireless Communication Systems.
550FPGA-Based VLSI Architecture for Real-Time Video Stabilization.
551Network-on-Chip Design for Enhanced Turbo Decoders.
552New Full Adder/Full Subtractor – Reversible Parity Preserving Optimal Design
553Implementation of Vedic Floating Point Multiplier on FPGA.
554Ultra large-Scale SoC Architectures Scan Test Bandwidth Management.
555High-Performance Network Processing through DDR3 Based Lookup Circuit.
556Implementations of Efficient 4-Bit Burst Error Correction for Memory Applications
557Cryptography Application: An Efficient Reversible LFSR Design.
558Twin Precision Multiplication Acceleration Design.
559Energy-Efficient VLSI Design for Real-Time Spike Sorting in Neural Signal Processing.
560SET-Based Digital to Time Converter Design.
561VLSI Architecture for a High-Performance Wavelet Packet Transform.
562Cache Update Trackers’ Area-Aware Design for Post Silicon Validation.
563A Dynamically Reconfigurable Multi-ASIP Architecture for Turbo Decoding.
564VLSI Design of Low-Power High-Resolution Sigma-Delta Modulators for Audio Applications.
565Optimized 1024 Point Radix-2 FFT Processor on FPGA for Improved Area and Frequency.
56610/100 Mbps Ethernet Switch Design for Networking Applications.
567Design and Implementation of Low-Power Configurable Booth-Multiplier.
568Fault Tolerant Bit-parallel Polynomial Basis Multiplication over GF(2m).
569A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO.
570Area-Efficient FPGA Implementation of a Deep Neural Network Accelerator.
571VLSI Architecture for High-Speed Computation of the Radon Transform in Medical Imaging.
572High-Speed Hardware 1D DCT/IDCT Implementation.
573RTL Implementation of AMBA ASB APB Protocol at System on Chip Level.
574Novel Hardware Architecture for Polynomial Matrix Multiplications in Reconfigurable Systems.
575Matching Architecture for Hard Systematic Error-Correcting Codes.
576Implementation of Lossless DWT/IDWT for Medical Images.
577Low Error, Energy-Efficient Fixed-Width Booth Multiplier with Conditional Probability Estimation.
578Rapid Sign Detection for the Residue Number System Moduli Set {2n+1 – 1, 2n – 1, 2n}.
579Memorization-Based Approximate Computing for Low-Power FPGA Design.
580Multi-Level 2D DWT Architecture without Off-Chip RAM for Low Complexity and Critical Path
581Fast Lock-in ADPLL for Dynamic Voltage and Frequency Scaling at 0.52/1 V.
582Fully Combinational Pipelined S-Box Implementation on FPGA.
583Efficient 3-D Discrete Wavelet Transform Architecture Design.
584Area–Delay–Power Efficient Carry-Select Adder Design.
585High-Performance VLSI Architecture for the LZW Compression Algorithm.
586Approximate Arithmetic Computing with Novel Data Format
587Low Redundancy Codes for Adjacent Error Correction with Parity Sharing
588Area-Delay-Power Considerations in RNS Reverse Converter Adder Placement Method.
589ASIC Design of a Low-Power High-Speed Chip-to-Chip Communication Interface.
590Design of a Low-Power VLSI Circuit for Real-Time PPG Signal Processing.
591Cross Parity Codes Architecture for Multiple Error Correction.
592Accurate Gaussian Random Number Generation in VLSI via the Central Limit Theorem.
593VLSI Design of a Compact and High-Speed Division and Square Root Unit.
594Communication System Power Optimization Using Clock Gating Technique.
595VLSI Design of a High-Speed Real-Time LiDAR Signal Processing Unit.
596Brent-Kung Adder-based Low Power and High-Speed Carry Select Adder.
597SEA Path Delay-Based Hardware Trojan Detection.
598NII Metric Compression in Memory-Reduced Turbo Decoding Architectures.
599Scalable Power Droop Reduction during Scan-Based Logic BIST
600VHDL Implementation of UART with Single Error Correction Capability.
601High-Speed ASIC Implementation of a Recursive Least Squares Adaptive Filter.
602Turbo Encoder Design and Simulation in Quantum-Dot Cellular Automata.
603FPGA Implementation of a Real-Time Lane Detection System for Autonomous Vehicles.
604Markov Random Field-Stochastic Logic-Based Low Power Area-Efficient DCT Implementation
605High-Performance ASIC Implementation of a Real-Time Multispectral Image Classification System.
606Reversible Watermarking Implementation for JPEG2000 Standard.
607Recursive Approach to Designing a Parallel Self-Timed Adder for Asynchronous Applications.
608Multiple-Bit-Error Correction: Cache-Assisted Scratchpad Memory Design.
609CMOS Active Inductor Design Methodology and Noise Analysis for High-Frequency Applications.
610A Low Power Reconfigurable Linear Feedback Shift Register (LFSR).
611RF Power Gating Technique for Low-Power Adaptive Radios.
612Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation for Low Error Energy Efficiency
613Design of a VLSI Architecture for Advanced Motion Estimation in Video Compression.
614Scalable Architecture for Montgomery Modular Multiplication with Low Latency.
615General Linear Feedback Shift Register (LFSR) Structures High Speed VLSI Architecture.
616FPGA-Based Implementation of a High-Speed Real-Time Spectrum Analyzer.
617Carry Select Adder with Area Delay Power Efficiency.
618Embedded Systems Code Compression Using Separated Dictionaries
619Multibit Flip-Flop Integration with Probability-Driven Clock Gating
620Aerospace Application Focused Area-Efficient and Reliable RHBD 10T Memory Cell Design
621Delta-G Modulo-(2^n Parallel Prefix n-3) Adder via Double Representation of Residues.
622Multi-cycle Tests Generation using LFSR
623Gigabit Ethernet MAC Transmitter Design.
624Parallel Sparse LU Factorization Method for Circuit Analysis Accelerated with GPU.
625Square Root Carry Select Adder in Modified Wallace Tree Multiplier.
626Energy-Efficient Approximate Multiplication for DSP and Classification Applications.
627Reconfigurable CORDIC: Conceptual Design and Implementation.
628Energy Efficiency in Speculative Look ahead Microprocessors.
629Improved Reversible Fault Tolerant LUT-Based FPGA Design.
630CNTFET-Based High-Performance Ternary Adder Design
631Scalable IoT Endpoint Devices with Near-Threshold RISC-V Core with DSP Extensions
632Functional Test Sequence Compaction Using Restoration-Based Procedures and Set Covering Heuristics.
633Factoring Technique Based Low-Power Design for Digit-Serial Polynomial Basis Finite Field Multiplier
634A Novel Approach for Add-Multiply Operator Design Using Modified Booth Recoding.
635Design of a High-Speed VLSI Architecture for 3D-DCT in Video Compression.
636MIPS Instruction Set Based Advanced Low Power RISC Processor Design.
637Exploration of Carry Propagation Free Compressors in Approximate Multiplier Designs
638FPGA Implementation of a Real-Time Multi-Filter Image Processing System.
639Energy Complexity Analysis in LDPC Decoder Circuits
640Design of a Low-Power VLSI Circuit for Real-Time Wireless Sensor Data Processing.
641VLSI Design of Low-Complexity Large Integer Multipliers for Homomorphic Encryption
642Adiabatic Logic Utilization in Combinational Coding Circuits for Energy Efficiency
643Advanced Microcontroller Bus Architecture (AMBA) Implementation for Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs).
644Enhanced Error Correction Codes for Multiple-Cell Upsets in Space Applications
645In-Field Structural Testing via Preemptive Built-In Self-Test.
646Reducing Energy Consumption in Network-on-Chip with Data Encoding Techniques.
647Sleep Convention Logic Design for Testability.
648FPGA Implementation of a High-Speed Real-Time Machine Vision System.
649Flexible Management of ECC for Transient Error Protection in Last-Level Caches.
650Efficient Binary Comparators Design in Quantum Dot Cellular Automata.
651Fixed Width Booth Multiplier with Conditional Probability for Accuracy Adjustment.
652RSD-Based ECC Processor: A High-Speed FPGA Implementation.
653Combinational Clock Gating Approach in Nanometer VLSI Circuits for Glitch-Free Operations.
654Novel Rectifying Encoder Solutions Based on Delta-Sigma
655Efficient Integer DCT Architectures for High Efficiency Video Coding.
656RS-232 System Controller Design.
657HUB Floating-Point Addition with Unbiased Rounding Technique
658Reconfigurable Multi-ASIP Architecture for Turbo Decoding in Diverse Communication Systems.
659AES Encryption and Decryption Algorithm Design with 128-bits Key Length.
660Enhancements in Floating-Point Systems Using HUB Formats for Round-to-Nearest Methods.
661Edge-Directed Video Up-scaler: High Efficiency VLSI Implementation.
662Design of a High-Performance VLSI Architecture for Over-the-Horizon Radar Signal Processing.
663VLSI Implementation of Median Filter Using Accumulative Parallel Counters.
664Hybrid-mode Floating Point Conversion Co-processor: HMFPCC.
665Advanced Clock-Gating Techniques for Low-Power Vector Processing in Fused Multiply-Add Operations
666Hybrid Architectures: LUT/Multiplexer in FPGAs.
667Neural Network Models in FPGA Logical Architecture Development.
668Multiple Chain Failures Diagnosis in Scan Chain Masking Environment.
669Network-on-Chip Data Encoding Techniques for Reducing Energy Consumption.
670Flip-Flop SRAM Cells with Single MTJ for Nonvolatile Performance.
671Energy-Efficient ASIC Design for a Wearable Real-Time Activity Recognition System.
672Ultra-Low-Voltage Wideband Low-Noise Amplifier Design Technique.
673High-Speed Modified TSPC D Flip-Flop with Low Power Design and Comparative Analysis
674Low Power Test Set Generation Using Functional Broadside Tests.
675Low-Latency Polar Decoder Architecture Using 2-Bit Decoding for Efficient Implementation.
676USB 2.0 Transceiver Macro-cell Interface (UTMI) Implementation.
677Penta MTJ-Based Combinational and Sequential Circuits: Low-Power Robust Easily Cascaded Designs.
678Coarse-Grained Reconfigurable Architectures: Memory-Aware Loop Mapping.
679Innovative Low Power 4-Bit Arithmetic Logic Unit Using Full-Swing GDI Technique
680Computing Reliability with Two Approximate Voting Schemes
681FPGA-Based VLSI Architecture for a Real-Time Depth Image-Based Rendering System.
682Energy-Efficient Approximate Multiplier with Logic Compression
683Stochastic Circuits Utilizing Parallel Sobol Sequences for Enhanced Energy Efficiency
684Composite Class-AB–AB Miller Op-Amp with High Gain and Stability
685Constant Matrix Multiplication Optimization for Low Power and High Throughput
686Implementing Hardware Algorithms for Binary Multiplication
687Design of a VLSI Architecture for Scalable Video Coding in Multimedia Applications.
688Design of Low-Power Pulse-Triggered Flip-Flop with Signal Feed-Through Scheme.
689ASIC Design of a Low-Latency Polar Decoder for 5G Communication Systems.
690Physical Design-Aware Synthesis of Fault-Tolerant Quantum Circuits.
691Sub-threshold Operation Analysis and Design of Classical CMOS Schmitt Trigger
692Approximate Booth Multiplier Design for Power Efficiency
693Scalable Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells.
694FPGA-Based Floating Point Multiplier Architectures Using DSP48E
695BCH Code Norm Syndrome Based Decoding for Error Correction Efficiency
696High-Speed Ternary Full Adder and Three Input XOR Circuits Using CNTFETs.
697High-Speed and Energy-Efficient Approximate Multiplier – RoBA
698Energy-Efficient VLSI Architecture for Deep Learning-Based Image Super-Resolution.
699Low Power Neural Signal Amplification in SCL 180nm Technology
700Enhancing NAND-Flash Memory with Array Dispersion LDPC Decoder Architectures.
701Built-in Self-Test Circuit for Droop Measurement in Digital Low-Dropout Regulators
702Double Precision Floating Point Multiplier Implementation Using VHDL on FPGA.
703CMOS Image Sensors: A Low-Power Incremental Delta–Sigma ADC.
704FM0/Manchester Encoding VLSI Architecture Using SOLS Technique for Dedicated Short Range Communications.
705Square Computation Dedicated Reversible Quantum Circuitry Design.
706Low-Power High-Speed Dual Modulus Prescalers with Branch-Merged TSPC Scheme.
707Encoder and Decoder Efficient Hardware Implementation for Golay Code.

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