The half-adder is extremely useful until you want to add more that one binary digit quantities. The slow way to develop a two binary digit adders would be to make a truth table and reduce it. Then when you decide to make a three binary digit adder, do it again. Then when you decide to make a four digit adder, do it again. Then when … The circuits would be fast, but development time would be slow.

Looking at a two binary digit sum shows what we need to extend addition to multiple binary digits.

11 11 11 --- 110

Look at how many inputs the middle column uses. Our adder needs three inputs; a, b, and the carry from the previous sum, and we can use our two-input adder to build a three input adder.

Σ is the easy part. Normal arithmetic tells us that if Σ = a + b + C_{in} and Σ_{1} = a + b, then Σ = Σ_{1} + C_{in}.

_{1}and C

_{2}? Let’s look at three input sums and quickly calculate:

Cin + a + b = ? 0 + 0 + 0 = 0 0 + 0 + 1 = 1 0 + 1 + 0 = 1 0 + 1 + 1 = 10 1 + 0 + 0 = 1 1 + 0 + 1 = 10 1 + 1 + 0 = 10 1 + 1 + 1 = 11

If you have any concern about the low order bit, please confirm that the circuit and ladder calculate it correctly.

In order to calculate the high order bit, notice that it is 1 in both cases when a + b produces a C_{1}. Also, the high order bit is 1 when a + b produces a Σ_{1} and C_{in} is a 1. So We will have a carry when C_{1} OR (Σ_{1} AND C_{in}). Our complete three input adder is:

For some designs, being able to eliminate one or more types of gates can be important, and you can replace the final OR gate with an XOR gate without changing the results.

We can now connect two adders to add 2 bit quantities.

A_{0} is the low order bit of A, A_{1} is the high order bit of A, B_{0} is the low order bit of B, B_{1} is the high order bit of B, Σ_{0}is the low order bit of the sum, Σ_{1} is the high order bit of the sum, and C_{out} is the Carry.

A two binary digit adder would never be made this way. Instead the lowest order bits would also go through a full adder.

There are several reasons for this, one being that we can then allow a circuit to determine whether the lowest order carry should be included in the sum. This allows for the chaining of even larger sums. Consider two different ways to look at a four bit sum.

111 1<-+ 11<+- 0110 | 01 | 10 1011 | 10 | 11 ----- - | ---- | --- 10001 1 +-100 +-101

If we allow the program to add a two bit number and remember the carry for later, then use that carry in the next sum the program can add any number of bits the user wants even though we have only provided a two-bit adder. Small PLCs can also be chained together for larger numbers. These full adders can also can be expanded to any number of bits space allows. As an example, here’s how to do an 8 bit adder.

_{xout}signals to move from A

_{0}+ B

_{0}up to the inputs of Σ

_{7}. If a designer builds an 8-bit adder as a complete device simplified to a sum of products, then each signal just travels through one NOT gate, one AND gate and one OR gate. A seventeen input device has a truth table with 131,072 entries, and reducing 131,072 entries to a sum of products will take some time. When designing for systems that have a maximum allowed response time to provide the final result, you can begin by using simpler circuits and then attempt to replace portions of the circuit that are too slow. That way you spend most of your time on the portions of a circuit that matter.

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